1. Technical Field
The present disclosure relates to fabrication technologies for semiconductor devices and, more particularly, to methods for manufacturing shallow trench isolation layers in semiconductor devices.
2. Background
As the fabrication technologies of semiconductor devices develop and the application areas of the semiconductor devices expand, efforts to improve the integrity of the devices have been widely made. For increasing the integrity of integrated circuit (IC) devices, miniaturizations of isolation layers in the devices has become especially important among others.
One of the conventional isolation technologies is Local Oxidation of Silicon (LOCOS) in which thick silicon oxide isolation layer grows selectively on a semiconductor substrate. However, the LOCOS layer has limitation in decreasing the width of the isolation layer because of the lateral diffusion of oxidation. Thus, in IC devices having submicron design rules, the use of LOCOS isolation is not proper.
The conventional Shallow Trench Isolation (STI) technology is used to overcome the drawbacks of the LOCOS technology by forming a shallow trench using an etching process in a semiconductor substrate and filling the trench with insulating material.
FIGS. 1a to 1g are cross-sectional views of the manufacturing process of the conventional STI isolation layer in a semiconductor device.
Referring to FIG. 1a, a pad oxide (SiO2 buffer layer) 12 having thickness of 100 Å to 200 Å grows by thermal oxidation on a silicon substrate 10. A silicon nitride (Si3N4) layer 14 having thickness of 1,000 Å to 2,000 Å is deposited as a hard mask on the pad oxide layer 12.
Referring to FIG. 1b, a moat pattern 16 that defines active and STI isolation areas is formed on the hard mask 14. The moat pattern 16 is formed by depositing a photo resist and exposing and developing the photo resist using the mask pattern of the STI.
Referring to FIG. 1c, the hard mask 14 and pad oxide 12 are patterned by a dry etching process with the use of the moat pattern 16. The dry etching of the hard mask 14 is performed by plasma dry etching of the target Si3N4 layer with an etchant gas of CHF3, O2 under Ar atmosphere in Magnetically Enhanced Reactive Ion Etching (MERIE) etching equipment. In this process, the flow rate of CHF3 gas is 40 surface cubic centimeters per minute (sccm) to 80 sccm, O2 gas is 0 sccm to 20 sccm, and Ar gas is 6 sccm to 120 sccm. The pressure of the MERIE equipment is 20 millitorr (mTorr) to 70 mTorr, and radio frequency (RF) power is 200 watts (W) to 300 W.
Then, as shown in FIG. 1d, the surface of the semiconductor substrate 10 exposed by the patterns of hard mask 14 and pad oxide 12 is dry etched by a predetermined depth, e.g., 3,000 Å to 5,000 Å to form a shallow trench 18 and the moat pattern 16 is removed.
On the inner walls of shallow trench 18 and the sides of pad oxide 12 and hard mask 14 a thin silicon oxide layer is formed as a liner insulating layer (not shown).
Referring to FIG. 1e, silicon oxide or Tetraetylorthosilicate (TEOS) is deposited as a gap-filling insulating layer to fill the shallow trench.
Then, as shown in FIG. 1f, Chemical Mechanical Polishing (CMP) is carried out to remove the gap-filling insulating layer 20 and liner insulating layer until the hard mark 14 is exposed. The CMP also planarizes the surface. Reference numeral 20a in the FIG. 1f represents the remaining gap-filling insulating layer after the CMP planarization process.
In FIG. 1g, the hard mask 14 is removed by phosphoric acid solution and the pad oxide 12 is partially removed by a cleaning process to form the final shallow trench isolation layer 20a. 
As described, the conventional STI process employs the hard mask and opens the hard mask to form the STI structure by using the hard mask. Unfortunately, the use of hard mask in the STI process results in the occurrence of Si nodule, which degrades the reliability and lowers the productivity of the semiconductor device.